In the latter half of the twentieth century, there began a phenomenon known as the information revolution. While the information revolution is a historical development broader in scope than any one event or machine, no single device has come to represent the information revolution more than the digital electronic computer. The development of computer systems has surely been a revolution. Each year, computer systems grow faster, store more data, and provide more applications to their users.
A modern computer system typically comprises one or more central processing units (CPUs) and supporting hardware necessary to store, retrieve and transfer information, such as communications buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication lines coupled to a network, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components.
From the standpoint of the computer's hardware, most systems operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. Programs which direct a computer to perform massive numbers of these simple operations give the illusion that the computer is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster.
A computer's CPU operates on data stored in the computer's addressable main memory. The memory stores both the instructions which execute in the processor, and the data which is manipulated by those instructions. In operation, the processor is constantly accessing instructions and other data in memory, without which it is unable to perform useful work. The design of the memory subsystem and speed at which it operates are critical issues in the overall performance of any computer system.
Memory is typically embodied in a set of integrated circuit modules. The time required to access memory is not only a function of the operational speed of the memory modules themselves, but of the speed of the path between the processor and memory. As computers have grown more complex, this path has consumed a larger share of the access time. Early computers had but a single processor and a relatively small memory, making the path between processor and memory relatively direct. Large modern systems typically contain multiple processors, multiple levels of cache, complex addressing mechanisms, and very large main memories to support the data requirements of the system. In these systems, it is simply not possible for direct paths to exist from every processor to every memory module. Complex bus structures support the movement of data among various system components. Often, data must traverse several structures between the processor and the actual memory module. This complexity not only affects access time, but the reliability of the memory subsystem as well. As the number of processors and size of memory grows, these issues become more acute.
Recently, there has been some interest in a memory architecture in which multiple buffered memory modules are configured in a daisy-chained arrangement. A command is passed from one module in the chain to the next, until it reaches its intended destination, and if data is to be returned, the returned data is passed back up the chain. Each link of the chain is a point-to-point link, typically comprising a pair of point-to-point unidirectional serial buses transmitting in opposite directions, each unidirectional serial bus going from a single module as sender to a single module as receiver. As used herein, a serial bus may have one, or more typically multiple, data lines, but requires multiple strobes of a bus clock (“bus beats”) to complete a single transaction. The data is divided at the sender and re-assembled at the receiver. A link could alternatively be a parallel bus, in which a single bus beat is required to complete the bus transaction.
The use of unidirectional point-to-point links has certain advantages in terms of bus clock speed and simplicity, since it does not require arbitration. However, there are certain limitations to this arrangement. The time to access a memory module increases in accordance with its position in the daisy chain, which places practical limitations on the length of the daisy chain. Additionally, a daisy chain arrangement may have a greater reliability exposure than, for example, a multi-drop bus, since a malfunction of a memory chip at the head of the daisy chain could effectively block access to all chips further down the chain.
A need exists for computer communications architectures having greater reliability and efficiency, and in particular for memory subsystem architectures supporting multiple memory modules having greater reliability and efficiency.